1. Field of the Invention
The present invention relates to an electron beam drawing process and an electron beam drawing apparatus and, more particularly, to an electron beam drawing process and an electron beam drawing apparatus capable of highly accurately superposition-exposing a pattern already drawn.
2. Related Art
In recent years, an electron beam drawing apparatus and an optical reduction exposure apparatus are used together to perform hybrid exposure thereby to manufacture an LSI having a multi-layered structure by drawing relatively fine patterns out of a plurality of patterned to be superposition-exposed by the electron beam drawing apparatus and by exposing the other patterns by the optical reduction exposure apparatus.
Here, the exposed pattern by the optical reduction exposure apparatus contains exposure distortion intrinsic to the lens of the optical reduction exposure apparatus and exposure error resulting from the circumferential change at the optical reduction exposure time. As a result, when a pattern is superposed and drawn as designed by the electron beam drawing apparatus on the pattern which has been exposed by the optical reduction exposure apparatus, there arises a problem that alignment error is caused between the patterns of the upper and lower layers.
In order to improve the alignment accuracy between the exposed pattern by the optical reduction exposure apparatus and the drawn pattern by the electron beam drawing apparatus, there has been disclosed in Japanese Patent Laid-Open No. 58621/1987 a process in which the position of a mark formed on a wafer by the optical reduction exposing apparatus is measured to determine the exposure distortion intrinsic to the optical reduction exposure apparatus so that drawing may be performed at the electron beam drawing time while correcting the exposure distortion. When adopting this process, however, in order to cope with the dynamic characteristic change of the optical reduction exposure apparatus, it is necessary to align all the chips on the wafer and to measure the marks frequently.
In Japanese Patent Laid-Open No. 186331/1982, there is disclosed another process in which marks sufficient to evaluate the exposure distortion are arranged in the peripheral portion of a pattern so that they are detected for correction at the drawing time. When adopting this process, however, the number of marks to be detected for evaluating the distortion is so large that the throughput cannot be improved.
In the optical reduction exposure method, on the other hand, in order to shorten the exposure time period, there is used an alignment method in which a mark at a designated point in a wafer is detected to correct the array information of chips in the entire wafer, as disclosed in Japanese Patent Laid-Open No. 169329/1987. This method has merits: (1) reduction of the influence of the mark detection error by a statistical method; and (2) shortening of the time period for detecting the marks. In this method, however, the correction is made only on the array information, and correction of the magnification change and rotation of the chips is finely adjusted manually in view of the exposure results.